1. Field of the Invention
The present invention relates to a memory module having a semiconductor memory chip.
2. Description of the Related Art
Conventionally, there is known a memory module in which memory IC chips are layered. Representative memory modules are disclosed in Japanese Patent Laid-Open No. 06-291250 (hereinafter, called Patent Document 1) and Japanese Patent Laid-Open No. 2004-327474 (hereinafter, called Patent Document 2).
In the memory module disclosed in Patent Document 2, an IO (Input/Output) chip is laid on an interposer substrate, and a plurality of DRAM (Dynamic Random Access Memory) chips are layered on the IO chip. The DRAM chip is provided with a through-electrode for conducting an electric signal from one surface to the other surface. The IO chip transmits and receives a signal and data to/from the DRAM chip according to a signal that is input from the outside through the interposer substrate. At this time, the IO chip can transmit and receive data to/from any DRAM chip by the through-electrode in the DRAM chips.
According to the memory module disclosed in Patent Document 2, the through-electrode must be provided in the IO chip, and the method for manufacturing the IO chip requires that there be a process to form the through-electrode.
Further, concerning data input/output of the DRAM chip, the interposer substrate is determined in accordance with the data bus width, such as four bits or eight bits. Even if it is fabricated, as is, no information of the data bus width is transmitted to the IO chip. Though the interposer substrate that corresponds to the data bus width of four bits is used, when the IO chip is initially set to the data bus width of eight bits, the IO chip attempts to output data of the 8-bits data bus width through the interposer substrate. To prevent this problem from occurring, the IO chip must be replaced together with the interposer substrate in accordance with the data bus width, and thus the cost of manufacturing is increased.